Controlling within-die uniformity using doped polishing material

ABSTRACT

Various embodiments include methods and integrated circuit structures. In some cases, an integrated circuit (IC) structure includes: a substrate; a set of fin structures overlying the substrate, the set of fin structures including a substrate base and a silicide layer over the substrate base; an oxide layer located between adjacent fins in the set of fin structures; and a nitride layer over the set of fin structures, wherein a height of the nitride layer is substantially uniform across the set of fin structures.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to, and is divisional application of,currently pending U.S. patent application Ser. No. 15/160,409, filed onMay 20, 2016, which is hereby incorporated by reference in its entirety.

BACKGROUND

The subject matter disclosed herein relates to integrated circuitdevices. More particularly, the subject matter relates to processes informing integrated circuit devices.

As integrated circuit (IC) technologies have advanced, the size of thesedevices has correspondingly decreased. In particular, as devices arereduced in scale to comply with ever-smaller packaging, tighterconstraints are applied to their dimensions and spacings.

Smaller ICs call for greater uniformity within the die used to formseparate IC chips. For example, some product constraints may call forless than two nanometers (nm) of within-die uniformity. Theseconstraints may be particularly tough to meet in certain processingapproaches, e.g., in chemical-mechanical polishing (CMP), wheremacro-loading causes variations in the density of structures within thedie.

SUMMARY

Various embodiments include methods and integrated circuit structures.In some cases, a method of forming an integrated circuit structure caninclude: forming a mask over an oxide layer and an underlying set of finstructures, the set of fin structures including a plurality of fins eachhaving a substrate base and a silicide layer over the substrate base;implanting the oxide layer through an opening in the mask; removing themask; polishing the oxide layer overlying the set of fin structuresafter removing the mask to expose the set of fin structures; and forminga nitride layer over the set of fin structures.

A first aspect of the disclosure includes a method of forming anintegrated circuit structure, the method including: forming a mask overan oxide layer and an underlying set of fin structures, the set of finstructures including a plurality of fins each having a substrate baseand a silicide layer over the substrate base; implanting the oxide layerthrough an opening in the mask; removing the mask; polishing the oxidelayer overlying the set of fin structures after removing the mask toexpose the set of fin structures; and forming a nitride layer over theset of fin structures.

A second aspect of the disclosure includes a method of forming anintegrated circuit structure, the method including: forming a mask overan oxide layer and an underlying set of fin structures, the set of finstructures including a plurality of fins each having a substrate baseand a silicide layer over the substrate base; implanting the oxide layerthrough an opening in the mask with ions of at least one of carbon,phosphorous or boron; removing the mask; polishing the oxide layeroverlying the set of fin structures after removing the mask to exposethe set of fin structures; and forming a nitride layer over the set offin structures, wherein a height of the nitride layer is substantiallyuniform across the set of fin structures.

A third aspect of the disclosure includes an integrated circuit (IC)structure having: a substrate; a set of fin structures overlying thesubstrate, each of the set of fin structures including a substrate baseand a silicide layer over the substrate base; an oxide located betweenadjacent fins in the set of fin structures; and a nitride layer over theset of fin structures, wherein a height of the nitride layer issubstantially uniform across the set of fin structures.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of this invention will be more readilyunderstood from the following detailed description of the variousaspects of the invention taken in conjunction with the accompanyingdrawings that depict various embodiments of the invention, in which:

FIG. 1 is a flow diagram illustrating processes in a method according tovarious embodiments.

FIG. 2A shows a schematic cross-sectional view of a first region withina precursor structure, through a first set of fin structures, accordingto various embodiments.

FIG. 2B shows a schematic cross-sectional view of a second region in theprecursor structure of FIG. 2A, with the cross-section through a secondset of fin structures.

FIG. 3A shows a schematic cross-sectional view of a first region of astructure undergoing a process according to various embodiments, withthe cross-section through a first set of fin structures.

FIG. 3B shows a schematic cross-sectional view of a second region of thestructure of FIG. 3A, with the cross-section through a second set of finstructures.

FIG. 4A shows a schematic cross-sectional view of a first region of astructure undergoing a process according to various embodiments, withthe cross-section through a first set of fin structures.

FIG. 4B shows a schematic cross-sectional view of a second region of thestructure of FIG. 4A, with the cross-section through a second set of finstructures.

FIG. 5A shows a schematic cross-sectional view of a first region of astructure undergoing a process according to various embodiments, withthe cross-section through a first set of fin structures.

FIG. 5B shows a schematic cross-sectional view of a second region of thestructure of FIG. 5A, with the cross-section through a second set of finstructures.

FIG. 6A shows a schematic cross-sectional view of a first region of astructure undergoing a process according to various embodiments, withthe cross-section through a first set of fin structures.

FIG. 6B shows a schematic cross-sectional view of a second region of thestructure of FIG. 6A, with the cross-section through a second set of finstructures.

FIG. 7A shows a schematic cross-sectional view of a first region of astructure undergoing a process according to various embodiments, withthe cross-section through a first set of fin structures.

FIG. 7B shows a schematic cross-sectional view of a second region of thestructure of FIG. 7A, with the cross-section through a second set of finstructures.

FIG. 8A shows a schematic cross-sectional view of a first region of anintegrated circuit (IC) structure according to various embodiments, withthe cross-section through a first set of fin structures.

FIG. 8B shows a schematic cross-sectional view of a second region of thestructure of FIG. 8, with the cross-section through a second set of finstructures.

It is noted that the drawings of the invention are not necessarily toscale. The drawings are intended to depict only typical aspects of theinvention, and therefore should not be considered as limiting the scopeof the invention. In the drawings, like numbering represents likeelements between the drawings.

DETAILED DESCRIPTION

As noted, the subject matter disclosed herein relates to integratedcircuit (IC) devices. More particularly, the subject matter relates tocontrolling within-die uniformity in integrated circuit devices.

As described herein, the term “within-die uniformity” refers to aconsistency in height and/or density of layers within a given die. As isknown in the art, in the process of forming IC devices, material layersare often formed, modified, etc. over a large wafer, which is then cut(or diced) to form individual pieces, each of which is called a die.

In contrast to conventional approaches, various embodiments of thedisclosure include approaches for forming nitride regions withsubstantially uniform heights within a layer of an IC structure ordevice. That is, according to various embodiments, approaches describedherein can control (e.g., enhance) within-die uniformity (e.g., heightuniformity in silicide layers) in IC structures.

In the following description, reference is made to the accompanyingdrawings that form a part thereof, and in which is shown by way ofillustration specific embodiments in which the present teachings may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the present teachings and itis to be understood that other embodiments may be utilized and thatchanges may be made without departing from the scope of the presentteachings. The following description is, therefore, merely illustrative.

As described herein, “depositing” may include any now known or laterdeveloped techniques appropriate for the material to be depositedincluding but are not limited to, for example: chemical vapor deposition(CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD),semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapidthermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reactionprocessing CVD (LRPCVD), metalorganic CVD (MOCVD), sputteringdeposition, ion beam deposition, electron beam deposition, laserassisted deposition, thermal oxidation, thermal nitridation, spin-onmethods, physical vapor deposition (PVD), atomic layer deposition (ALD),chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

FIG. 1 is a flow diagram illustrating processes performed according tovarious embodiments of the disclosure. FIGS. 2A, 2B through 8A, 8B showschematic cross-sectional depictions of regions of integrated circuitstructures (and precursor structures) that illustrate processesperformed according to various embodiments. It is understood that theprocesses outlined herein may be performed in a different order thandescribed in some embodiments. Additionally, not all of the processesoutlined herein need necessarily be performed according to variousembodiments.

Turning to FIGS. 2A, 2B through 8A, 8B, with continuing reference toFIG. 1, schematic depictions of processes of forming an integratedcircuit (IC) structure 26 (FIG. 8A and FIG. 8B) performed on a firstregion 1 of a precursor structure 2 (FIGS. 2A) and a second region 3 ofprecursor structure 2, are shown according to various embodiments.Figures labeled “A” depict first region 1, which includes ahigher-density region (with greater number of fins 8) relative to alower-density region (second region 3), labeled in Figures “B.” As shownin FIGS. 2A and 2B, precursor structure 2 can include an oxide layer 4over a set of fin structures 6, where the underlying set of finstructures 6 can include a plurality of fins 8 having a substrate base10 and a silicide layer 12 overlying substrate base 10. In variousembodiments, oxide layer 4 can include silicon dioxide (SiO₂). FIGS.2A-7B illustrate processes, with respect to two distinct regions 1, 3(cross-section across fins 8).

Substrate base 10 can be formed (e.g., etched) from a substrate 12,which may include silicon, doped silicon or silicon germanium. In somecases, substrate 12 can include on or more substrate materials such assilicon, germanium, silicon germanium, silicon carbide, and thoseconsisting essentially of one or more III-V compound semiconductorshaving a composition defined by the formulaAl_(X1)Ga_(X2)In_(X3)As_(Y1)P_(Y2)N_(Y3)Sb_(Y4), where X1, X2, X3, Y1,Y2, Y3, and Y4 represent relative proportions, each greater than orequal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relativemole quantity). Other suitable substrates include II-VI compoundsemiconductors having a composition Zn_(A1)Cd_(A2)Se_(B1)Te_(S2), whereA1, A2, B1, and B2 are relative proportions each greater than or equalto zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore,a portion or entire substrate 12 may be strained. In variousembodiments, e.g., where substrate 12 includes a doped silicon,substrate 12 can include elemental semiconductor materials (e.g.,silicon, germanium, carbon, or alloys thereof), III-V semiconductormaterials, or II-VI semiconductor materials. According to variousembodiments, the (doped) silicon substrate 12 is deposited as a bulksilicon, and subsequently ionized to dope the bulk silicon material. Inother cases, a portion of substrate 12 is ionized (e.g., subjected toionizing radiation) to form a doped silicon layer. In variousembodiments, a conventional masking and etching process can be employedto form fins 8, e.g., from substrate base 10, e.g., including forming ahard mask over substrate base 10 and etching the underlying silicon(e.g., doped silicon) using the mask to remove portions of substratebase 10 between plurality of fins 8. It is understood, however, thatfins 8 can be formed according to various approaches known in the art.In non-limiting examples, fins 8 can be formed by epitaxially growing atleast a portion of fins 8 over substrate 12, by patterning portions offins 8 over substrate base 12, etc.

As shown, processes according to various embodiments can include:

Process P1A (an optional pre-process according to various embodiments),which is illustrated in FIGS. 2A-2B and 3A-3B, including: polishingoxide layer 4, wherein oxide layer 4 includes surface contours 14 (FIGS.2A, 2B) prior to the polishing (FIG. 3A, 3B). In various embodiments,surface contours 14 can include bumps or protrusions forming an unevenupper surface of oxide layer 4. In various embodiments, polishing oxidelayer 4 includes performing a conventional chemical mechanical polishing(planarization) technique known in the art, e.g., using a polishingdevice and a chemical slurry to remove portions of oxide layer 4. Asshown in FIGS. 2A and 2B, prior to polishing, surface contours 14 mayexist due to the formation of oxide layer 4 over underlying fins 8 andspaces between those fins 8. Surface contours 14 can correspond with adensity of fins 8 in a particular region, for example, first region 1may have a greater concentration of surface contours 14 due to itshigher density of fins 8 when compared with second region 3.

Process P1 (following process P1A, in various embodiments, illustratedin FIGS. 3A and 4A): forming a mask 16 over oxide layer 4 and anunderlying set of fin structures 8. In various embodiments, mask 16 caninclude a conventional photoresist and/or hardmask material, such as anitride, e.g., a silicon nitride. In some cases, mask 16 is depositedover oxide layer 4 using conventional deposition techniques, however, inother cases, mask 16 may be epitaxially grown or otherwise formed overoxide layer 4. In some cases, mask 16 may be formed using conventionalphotolithography techniques, including but not limited to deepultraviolet (DUV) or extreme ultraviolet (EUV) processes, sidewallimaging transfer processes, or multiple patterning processes. In variousembodiments, as shown in the side-by-side comparison of FIGS. 4A and 4B,mask 16 may be selectively formed over only a region (e.g., first region1) and not formed over other region(s) (e.g., second region 3).

Process P2 (illustrated in FIGS. 5A and 5B): implanting (with ions 17)oxide layer 4 through an opening 18 in mask 16. As shown in FIGS. 5A and5B, mask 16 can be formed over fins 8 in first region 1, leaving finstructures 6 in second region 3 (e.g., in regions having a lowerconcentration of fins 8, where fins 8 are adjacent large oxide regions20) exposed via opening(s) 18. In various embodiments, oxide 4 and oxideregions 20 (e.g., separating adjacent sets of fin structures 6) areimplanted with ions 17 via conventional ion-implant techniques. Mask 16can prevent implanting in underlying regions of oxide 4 and fins 8. Insome cases, ion implanting is performed with ions of at least one ofcarbon (C), phosphorous (P) or boron (B). Use of C, P or B ions forimplanting can reduce the subsequent removal rate (e.g., polishing rate)of oxide 4 in second region 3 when compared with non-implanted oxide 4in first region 1.

Process P3 (shown as post-implanted depiction in FIGS. 6A and 6B):removing mask 16, e.g., via conventional etching techniques such as wetetching or dry etching. In some cases, mask 16 can be removed from firstregion 1 using a chemical etching process. For example, remaining mask16 can be removed, e.g., by dry plasma ashing or (selectively) wetcleaning (e.g., using sulfuric peroxide). As shown, a portion 21 ofoxide layer 4 in second region 3, previously exposed between mask(s) 16,is implanted with ions.

Process P4 (FIGS. 7A, 7B): polishing oxide layer 4 overlying set of finstructures 6 after removing mask 16 to expose an upper surface 23 theset of fin structures 6. In various embodiments, polishing oxide layer 4includes performing a conventional chemical mechanical polishing(planarization) technique known in the art, e.g., using a polishingdevice and a chemical slurry to remove portions of oxide layer 4. Insome cases, polishing is performed in a single process across firstregion 1 and second region 3, such that additional processing is notnecessary for lower-density regions (e.g., second region 3) versushigher-density regions (e.g., first region 1)

Process P5 (FIGS. 8A, 8B): forming a nitride layer 22 over the set offin structures 6. In various embodiments, nitride layer 22 can includesilicon nitride (SiN). According to some embodiments, forming nitridelayer 22 can include forming (e.g., depositing) a silicon (e.g., thinlayer) over the exposed set of fin structures 6 and a remaining portion24 of oxide layer 4, and exposing the silicon to nitrogen and heat toconvert the silicon to SiN. According to various embodiments, implantingoxide 4 in large oxide regions 20, e.g., in lower-density region (secondregion 3), can reduce the removal rate of the oxide 4 in these regions,and allow for level formation of nitride layer 22 across a wide gapbetween adjacent fins 8.

That is, the polishing process (P4) is a significant process in reducingfree oxide residue within oxide layer 4. However, as noted herein, wherelarge oxide regions are present, such as oxide 4 in second region 3, themacro-loading from polishing can cause conventional oxide structures topolish at different, undesirably fast, rates. According to variousembodiments herein, oxide 4 in these regions (e.g., large oxide regions20 in second region 3) is ion implanted to reduce the removal (e.g.,polish) rate of that oxide 4 relative to oxide 4 in more densely-packedregions (e.g., first region 1). By reducing the removal rate of largeoxide regions 20 in second region 3 relative to oxide 4 in first region1, a more uniform upper surface can be formed between the two regions 1,3, allowing for level formation of nitride layer 22 in IC structure 26.

According to various embodiments, as shown in the IC structure 26 inFIGS. 8A and 8B, a height (h) of nitride layer 22 is substantiallyuniform across set of fin structures 6, e.g., nitride layer 22 has asubstantially uniform thickness across fin structures 6 and oxide 4. Inother words, as measured across a flat plane (p), the substantiallyuniform height (h) is defined as having a deviation of less thanapproximately 2 nanometers across nitride layer 22 over the set of finstructures 6 and oxide 4. As noted herein, forming nitride layer 22 suchthat it has a height uniformity in IC structure 26 can help to overcomeperformance issues associated with non-uniform density in conventionalintegrated circuits.

It is understood that the herein-noted approaches can be implemented inany stage of integrated circuit formation, e.g., front-end of line(FEOL), back-end of line (BEOL) and/or middle of line (MOL) processes.As is known in the art, FEOL can include operations performed on thesemiconductor wafer in the course of device manufacturing up to firstmetallization, BEOL can include operations performed on thesemiconductor wafer in the course of device manufacturing followingfirst metallization, and MOL can include operations performed on thesemiconductor wafer during first metallization.

When an element or layer is referred to as being “on”, “engaged to”,“connected to” or “coupled to” another element or layer, it may bedirectly on, engaged, connected or coupled to the other element orlayer, or intervening elements or layers may be present. In contrast,when an element is referred to as being “directly on,” “directly engagedto”, “directly connected to” or “directly coupled to” another element orlayer, there may be no intervening elements or layers present. Otherwords used to describe the relationship between elements should beinterpreted in a like fashion (e.g., “between” versus “directlybetween,” “adjacent” versus “directly adjacent,” etc.). As used herein,the term “and/or” includes any and all combinations of one or more ofthe associated listed items.

Spatially relative terms, such as “inner,” “outer,” “beneath”, “below”,“lower”, “above”, “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. Spatiallyrelative terms may be intended to encompass different orientations ofthe device in use or operation in addition to the orientation depictedin the figures. For example, if the device in the figures is turnedover, elements described as “below” or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.Thus, the example term “below” can encompass both an orientation ofabove and below. The device may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the disclosure.As used herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof. It is further understood that theterms “front” and “back” are not intended to be limiting and areintended to be interchangeable where appropriate.

This written description uses examples to disclose the invention,including the best mode, and also to enable any person skilled in theart to practice the invention, including making and using any devices orsystems and performing any incorporated methods. The patentable scope ofthe invention is defined by the claims, and may include other examplesthat occur to those skilled in the art. Such other examples are intendedto be within the scope of the claims if they have structural elementsthat do not differ from the literal language of the claims, or if theyinclude equivalent structural elements with insubstantial differencesfrom the literal languages of the claims.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiments, the practical application or technicalimprovement over technologies found in the marketplace, or to enableothers of ordinary skill in the art to understand the embodimentsdisclosed herein.

We claim:
 1. An integrated circuit (IC) structure comprising: asubstrate; a set of fin structures overlying the substrate, the set offin structures including a substrate base and a silicide layer over thesubstrate base; an oxide layer located between adjacent fins in the setof fin structures; and a nitride layer over the set of fin structures,wherein a height of the nitride layer is substantially uniform acrossthe set of fin structures.
 2. The IC structure of claim 1, wherein theoxide layer includes silicon dioxide (SiO₂) and is doped with at leastone of carbon, phosphorous or boron, and wherein the nitride layerdirectly contacts the set of fin structures.
 3. The IC structure ofclaim 1, wherein the substantially uniform height is defined as having adeviation of less than approximately 2 nanometers across the nitridelayer over the set of fin structures.
 4. The IC structure of claim 1,wherein the nitride layer includes silicon nitride (SiN).